Imec Introduces New Pathfinding PDK for Cutting-Edge Semiconductor Technologies

Imec, the prestigious nanoelectronics research centre, has recently announced the launch of a new Process Design Kit (PDK) aimed at advancing digital designs within their N2 technology. This significant development was unveiled during the IEEE International Solid-State Circuits Conference (ISSCC) and is anticipated to revolutionise the approach of chip designers to their work.

The integration of the PDK into EDA tool suites, such as those from Cadence Design Systems and Synopsys, will offer a diverse range of options for advanced nodes for design pathfinding, system research, and training. This level of access will equip both academia and industry with the essential tools needed to transition their products into the next generation of technologies.

Traditionally, Foundry PDKs offer chip designers a library of tested and approved components to deliver reliable designs. However, limited access and the requirement for NDAs have created barriers for academia and industry to access advanced technology nodes during their development. The unveiling of Imec’s N2 PDK is projected to significantly reduce these barriers, providing a welcomed breakthrough for both academia and commercial companies.

Julien Ryckaert, VP Logic Technologies at Imec, emphasised the importance of providing early access to infrastructure to develop design skills on the most advanced technology nodes. “If we want to engage a new generation of chip designers, we must provide them early access to the infrastructure needed to develop their design skills on the most advanced technology nodes,” Ryckaert stated. This, along with the accompanying training courses, will prepare designers and companies alike for future technology nodes and enable them to anticipate scaling bottlenecks for their products.

The design pathfinding PDK comprises the necessary infrastructure for digital design, based on a set of digital standard cell libraries and SRAM IP macros. Moving forward, the plan is to extend the PDK platform to even more advanced nodes such as A14. The training program is set to commence in early Q2, imparting subscribers with the specificities of the N2 technology node and offering hands-on training on digital design platforms using Cadence and Synopsys EDA software.

Brandon Wang, vice president, technical strategy & strategic partnerships at Synopsys, acknowledged the significance of nurturing an engineering workforce that is equipped with the necessary technology to create transformational products, stating, “Imec’s design pathfinding PDK is an excellent example of how industry partnerships can broaden access to advanced process technology for the current and next generation of designers to accelerate their semiconductor innovation.”

In conclusion, Imec’s latest endeavour has the potential to significantly reshape the landscape for chip designers, opening up a world of possibilities for the development of cutting-edge semiconductor technologies. This collaborative effort with industry leaders is a crucial step towards ensuring that the next generation of designers is well-prepared to drive innovation and propel the semiconductor industry into the future.