The ESD Association (ESDA) has recently unveiled its latest technology roadmap, aimed at offering guidance and support to professionals in the field of electrostatic discharge (ESD) and latch-up. This roadmap is targeted towards industry and academic experts globally, providing insights into the future ESD thresholds for semiconductor devices and their impact on ESD control practices. Furthermore, it addresses existing and potential technical challenges in the realm of ESD and latch-up. The most recent edition of the roadmap was released in January 2024, and the expertise and vision of the ESDA Advanced Topics Team were instrumental in its development [1].
ESD Target Level
The evolution of Charged Device Model (CDM) target levels has witnessed notable changes over time. For instance, CDM target levels for ultra high-speed IO applications have decreased from 500 V to 125 V with advancements in technologies. It is important to note that the achievable level can range from 500-125V, depending on IC design functions, and it is projected to decrease even further in the coming decade. The current target levels for Human Body Model (HBM) and CDM are set at 1kV and 250V respectively, with no anticipated changes until 2030. The attainable CDM protection level is influenced by factors such as IO design, type, and package size effects [2].
ESD Testing
The commonly used field-induced CDM testing has encountered limitations with larger variability when applying low-stress levels and decreasing pin pitches. In response, the ESDA JEDEC CDM Joint Working Group is presently evaluating two contact CDM stress methods: low impedance-contact CDM (LICCDM) and capacitively coupled Transmission Line Pulse (cc-TLP). Both methods allow for the application of low CDM stress levels to small pin pitches and have shown a strong correlation with CDM results in various studies, offering a reliable means to stress small pin pitches [2].
Outlook
The future of CMOS technologies is gravitating towards nanowire- or nanosheet-based device architectures, accompanied by an increasing use of compound semiconductors such as Gallium Nitride and Silicon Carbide, especially in energy conversion. This transition also encompasses the integration of photonic technologies to facilitate the extensive data bandwidths demanded by the digital society. Electronic Design Automation (EDA) tools for design verification will play a pivotal role in supporting ESD and latch-up protection design, while the escalating computational power and new machine learning methods will enable the simulation and verification of complex IC designs. Advanced packaging is also poised for significant advancements, particularly in the development of separate dies or chiplets connected in a single package, posing new challenges in terms of ESD control and mitigation [3].
Summary
The ESDA technology roadmap stands as a crucial guiding document for ESD and latch-up experts in the global industry and academia. The recent edition of the roadmap has illuminated the ESD target levels and a major industry trend. Ongoing work on this roadmap is already underway, with the next edition expected to be published by the next EOS/ESD Symposium in September 2024.